The present major trend in semiconductor fabrication is moving towards integration of 3D IC chip or die packages having vertically stacked chips and direct electrical inter-chip connections in lieu of other interconnect techniques such as wire bonds and chip edge interconnects. The dies in such 3D IC chip packages may include fine (small) pitch vertical through substrate vias (TSVs) which may be used to form a direct electrical connection to an adjoining stacked die. TSVs offer higher density interconnects and shorter signal paths creating the possibility of forming die packages having smaller form factors and thin die stacks. The TSVs in top dies may be terminated on the back side with very fine pitch microbump arrays for final interconnection to and mounting on a semiconductor substrate.
In 3D IC chip packages, interposers may be used to make electrical connections between adjoining dies or between die packages and another semiconductor substrate which may include various electrically conductive interconnects such as redistribution layer (RDL) structures in some embodiments that may be used to increase or decrease the pitch spacing of the electrical contacts to aid with eventual final mounting of the chip package on another substrate, which may be a package printed circuit board (PCB), packaging substrate, high-density interconnect, or other.
A further current trend is to incorporate TSVs into interposers making them compatible with 3D IC chip package integration. Since the interposers form part of the stacked chip or die package, it is desirable to make the interposers as thin as possible to minimize the height of the chip package.
An improved process for making a thin interposer is desired.
All drawings are schematic and are not drawn to scale.